Physical Design Engineer

Role Overview

Key Responsibilities

• Drive RTL synthesis and synthesis optimization to achieve performance, power, and area (PPA) objectives.
• Perform floorplanning for complex ASIC and SoC designs, considering timing, congestion, and power distribution requirements.
• Collaborate with RTL design engineers to improve RTL quality, synthesis results, and implementation efficiency.
• Analyze synthesized netlists to identify optimization opportunities and improve design quality.
• Work with architecture, RTL, verification, and physical design teams to support design convergence.
• Identify implementation bottlenecks and recommend improvements to facilitate timing closure.
• Participate in design reviews and contribute to improvements in design methodologies and implementation processes.

Required Skills & Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• 10+ years of industry experience in ASIC/SoC physical design.
• Strong hands-on experience with RTL synthesis and timing optimization.
• Solid experience in floorplanning for advanced technology nodes.
• Strong understanding of netlist optimization and physical implementation methodologies.
• Experience collaborating with RTL and design teams to improve design quality and implementation efficiency.
• Ability to work effectively across multidisciplinary silicon engineering teams.

Preferred Qualifications

• Experience with industry-standard EDA tools for synthesis and physical design.
• Strong understanding of timing, congestion, power, and area optimization techniques.
• Experience with placement optimization and PPA improvement methodologies.
• Background in high-performance CPU, GPU, AI/ML, or networking SoC designs.

Applicants will be asked to answer the following qualifying questions when applying for this position:

• 1Do you have 10+ years of hands-on experience in ASIC/SoC physical design, including RTL synthesis and timing optimization?
• 2Do you have hands-on experience with floorplanning, netlist optimization, and physical implementation for complex ASIC/SoC designs?
• 3Have you worked on placement optimization and PPA (Power, Performance, and Area) optimization in advanced semiconductor design projects?
• 4Are you legally authorized to work in the United States? We consider candidates with valid work authorization under any visa category, except those relying on OPT.