ASIC Design Verification (DV) & UVM Engineer

Role Overview

Key Responsibilities

• Define, develop, and execute comprehensive verification strategies and test plans at both IP and SoC levels.
• Architect and implement scalable, reusable constrained-random verification environments using SystemVerilog and UVM.
• Develop verification environments for RF payloads, satellite processors, and communications systems.
• Verify PCIe Gen 3–6 subsystems across Physical, Data Link, and Transaction layers.
• Verify high-throughput DMA engines and PCIe Endpoint and Root Complex configurations.
• Develop and execute tests for high-speed industry-standard protocols and specification compliance.
• Perform functional, performance, and low-power verification where applicable.
• Debug complex simulation failures and perform root-cause analysis at the RTL level.
• Develop coverage-driven verification strategies and track functional and code coverage.
• Set up and execute gate-level simulations with or without timing annotations.
• Collaborate with RTL design, architecture, and verification teams to identify and resolve issues.
• Create verification automation and infrastructure using scripting languages and industry-standard verification tools.

Required Skills & Qualifications

• 8+ years of hands-on experience in ASIC/SoC Design Verification.
• Strong expertise in SystemVerilog and UVM.
• Proven experience developing constrained-random, reusable verification environments from scratch.
• Strong IP and SoC-level verification experience.
• Hands-on experience with PCIe and DMA verification.
• Strong understanding of protocol verification and specification compliance.
• Hands-on experience with gate-level simulation and RTL-level debugging.
• Proficiency in at least one verification scripting language: Python, Perl, or Tcl.
• Experience with industry-standard simulators such as VCS, Xcelium, or Questa.
• Bachelor's or Master's degree in Electrical Engineering, Electronics & Communication, VLSI, Computer Engineering, or a related field.
• Experience with PCIe Gen 3/4/5/6.
• Knowledge of low-power verification using UPF/CPF and/or performance verification.
• Strong coverage-driven verification methodology experience.
• Experience with RF, satellite, aerospace, processor, or communications systems.
• Experience verifying complex SoC subsystems and high-bandwidth interfaces.
• Experience working in highly complex ASIC/SoC development environments.

Applicants will be asked to answer the following qualifying questions when applying for this position:

• 1Are you legally authorized to work in the United States without visa sponsorship?
• 2Do you have 8+ years of hands-on ASIC/SoC Design Verification experience with strong SystemVerilog and UVM expertise?
• 3Do you have hands-on experience verifying PCIe Gen 3/4/5/6 subsystems and DMA engines at the IP or SoC level?